DRAM Layout Engineer - IP Layout & Verification
Micron Memory Malaysia Sdn Bhd
Micron Technology, Inc. is seeking a DRAM Design Tech Layout Engineer in Tlaquepaque, Jalisco, Mexico.
You will translate schematics into layout suitable for fabrication reticles and work with Design and other engineering groups to apply various layout techniques for digital and analog circuits. Responsibilities include IP layout development, layout verification (LVS/DRC/EM), and ensuring on‑time delivery of high‑quality layouts.
#J-18808-LjbffrVacante publicada el 4 días atrás
Empleos similares que podrían interesarleBasado en la vacante DRAM Layout Engineer - IP Layout & Verification en Tlaquepaque, Jal.
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Tlaquepaque, Jal.2 días atrás
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