Principal / Staff FPGA Engineer — Communications Test & Measurement

We are seeking a Principal/Staff-level FPGA Engineer and technical authority to own the end-to-end FPGA architecture for our next-generation Communications Test & Measurement products.

In this role, you will drive critical architectural decisions—from make/buy IP tradeoffs to floorplanning and timing closure strategies for multi-gigabit designs. As the final technical escalation point, you will mentor engineers, lead complex debug efforts, and guide products from architecture all the way through volume production.

Key Responsibilities

• Architectural Ownership: Define and drive end-to-end FPGA architecture, including DFX approaches and IP evaluation.
• High-Speed Design & Timing: Own floorplanning, multi-gigabit transceiver integration, and advanced timing closure strategies for complex designs.
• Technical Leadership & Escalation: Serve as the ultimate technical authority for FPGA design, acting as the primary escalation point for team debug issues.
• Bring-Up & Root Cause Analysis: Lead hands-on root-cause debug for silicon, board bring-up, and link-layer issues across high-speed protocols.
• Mentorship: Elevate the engineering team by mentoring peers and communicating high-level architecture decisions to global stakeholders.

What You’ll Bring (Mandatory Requirements)

• Education & Experience: BS or MS in Electrical/Computer Engineering with 12–15+ years of relevant experience, including 5+ years specifically architecting and closing timing on multi-Gbps SerDes/transceiver-based designs.
• HDL Mastery: Demonstrated expertise implementing high-speed designs using Verilog, SystemVerilog, and/or VHDL .
• Transceiver Expertise: Deep, hands-on experience with FPGA transceivers, hard IP, PLLs, equalization, and multi-Gbps link debug.
• Networking & Protocols: Proven experience with high-speed Ethernet (10M to 1.6T ), IP protocol stacks, optical interfaces (SFPs, QSFPs), VLANs, MPLS, VPLS, and VoIP/IPTV.
• Toolchain & Device Mastery: Extensive production experience with AMD or Altera devices and their full implementation toolchains (advanced floorplanning and timing closure).
• Advanced Verification: Proven background in formal verification and/or UVM-based verification methodologies .
• Product Lifecycle: Track record of taking complex FPGA designs from architecture through volume production, including HW/FW boundary tradeoffs.
• Communication: Exceptional written and verbal communication skills with a proven ability to mentor and lead globally distributed teams.