Senior Layout Desig Dram (San Pedro Tlaquepaque)

Job Summary

Micron Technology is seeking a senior VLSI / Layout Engineer to work on critical IP design and verification in a hybrid location based in Mexico. This role involves working closely with design engineers on floor planning, layout design, and verification protocols in Cadence VLE/VXL and Calibre DRC/LVS environments.

Responsibilities

• Use Cadence VLE/VXL and Calibre DRC/LVS to support layout and verification tasks.
• Collaborate with design engineers to floor plan and design layout.
• Follow verification protocols and ensure design compliance.
• Understand and apply tape‑out processes, DFM, and OPC.
• Document design methodology and interface with design engineers to clarify layout requirements.
• Organize, prioritize, and manage logistics and resources for project deliverables.
• Develop methodologies to resolve issues and guide layout designers toward technical and professional development.

Requirements

• Minimum 6 years of experience with Cadence VLE/VXL and Calibre DRC/LVS.
• Basic understanding of circuit design.
• Understanding of tape‑out processes, DFM, and OPC.
• Proven ability to manage task prioritization to meet schedules and deadlines.
• Strong communication skills for interaction with design engineering teams.
• BE or MTech in Electronic/VLSI Engineering or related field; Mechatronics acceptable.

Location

Hybrid position located in Mexico.

EEO Statement

Micron is an equal opportunity employer. Micron prohibits the use of child labor and complies with all applicable laws, rules, regulations, and industry labor standards.