Memory & DRAM Design Verification Engineer

Link-Worldwide

Link-Worldwide is looking for a Design Verification Engineer located in Mexico, Jalisco, Región Centro. In this role, you will design and verify high-density memory chips while collaborating on innovative verification tools with an international team.

The ideal candidate will have a BS or MS in Electrical Engineering or Computer Engineering with a strong understanding of CMOS design. Knowledge of programming in Python and debugging skills are essential.

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Vacante publicada el 2 días atrás

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