Senior Engineer - Hbm Verification Tlaquepaque, Jalisco, Mexico (San Pedro Tlaquepaque)

SENIOR ENGINEER - HBM VERIFICATION

Tlaquepaque, Jalisco, Mexico

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Unique Opportunities

• Complete ownership of verification and end-to-end analysis of complex full chip custom designs with advanced low power and power management technologies spread across multiple categories such as memories that are capable of operating at high speeds.
• Collaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design.
• Work on cross functional tasks that can widen your skill set.

Responsibilities

• Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes.
• Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs.
• Develop Test cases/Stimulus to increase the functional coverage for HBM emerging memory architectures and features.
• Participate in developing verification methodology and verification environments for advanced HBM and emerging memory products.
• Co-work with international colleagues on developing new verification flows to take on the challenges in HBM and emerging memory design.
• Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements.

Minimum Qualifications

• 5+ years of experience in pre-silicon verification
• BE or MTech in Electronics Engineering, or related.
• Proficiency in establishing and simulating verification environments
• Proficient understanding of basic digital circuits, simulation, troubleshooting, and evaluation.
• Proven ability to guide and direct verification efforts within areas of expertise.
• Experience developing test cases/stimuli to increase functional coverage

Preferred Qualifications

• Experience with high-level understanding of UVM.
• Knowledge of DFT features, including custom DFT and standard scan chains.
• Exposure to critical timing, data path timing analysis.
• Experience with complete ownership of verification and end-to-end analysis of complex full chip custom builds with outstanding power, performance, and bandwidth.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.