Senior DRAM Layout & IP Verification Engineer
Link-Worldwide
Link-Worldwide in Mexico, Jalisco is actively looking for a talented DRAM Design Engineer to transform schematics into fabrication layouts. This role includes designing IP layouts, verifying the quality of layouts, and ensuring projects are delivered on time.
The ideal candidate will hold a Bachelor's degree in Electrical or Electronics Engineering and have over 3 years of experience in advanced CMOS layout design. Strong problem-solving skills and proficiency in Cadence tools are necessary.
#J-18808-LjbffrVacante publicada el 1 día atrás
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