Senior Design Engineer

We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver high-performance, and power-efficient processors.

Utilize back-end EDA tool flows, develop/optimize methodologies for synthesis, place-and-route (PnR), clock tree synthesis (CTS), and timing closure.

Work closely with RTL designers to improve timing, area and power efficiency, and evaluate design changes and their impact on PPA.

Perform static timing analysis (STA), power analysis, signal integrity checks, and DFT implementation.

Optimize floorplanning, clock distribution, power delivery networks, and congestion reduction strategies.

Automate design flows and methodologies to improve efficiency and scalability.

Bachelor’s/Master’s/PhD in Electrical Engineering, Computer Engineering, or related field.

• 4+ years of experience in physical design of complex ASICs or CPUs.
• Strong expertise in Physical Design methodologies, tool flows, and PPA trade-offs.
• Proficiency with EDA tools such as Synopsys (ICC2, Design Compiler, PrimeTime), or Cadence (Innovus, Genus, Tempus).
• Solid knowledge of place-and-route, clock tree synthesis, timing closure, and physical verification.
• Hands‑on experience with power analysis, leakage optimization, ECO implementation and equivalence sign‑off.
• Proficiency in reading RTL (Verilog/VHDL) and understanding logic design.
• Strong scripting skills in Python, Tcl, or Perl for tool automation and data analysis.
• Understanding of low‑power design techniques such as clock gating, power gating, multi‑Vt optimization and multi‑power domain.

A flexible and inclusive work culture based in Guadalajara, Mexico.

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