DRAM IP Layout Intern: Design & Automation
Micron Technology, Inc
Micron Technology, Inc in Mexico is seeking a Layout Design Engineering Intern to contribute to the development and verification of IP layout cells used in memory products. You will work with experienced layout engineers on floorplanning, placement, routing, and physical verification.
You will also explore automation via scripting and AI-supported development to improve productivity and design quality, with opportunities to learn EDA tools such as Cadence or Synopsys.
#J-18808-LjbffrVacante publicada el 2 días atrás
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Tlaquepaque, Jal.2 días atrás - ...Job Title JR101719 – DRAM Design Tech Layout Engineer Position Level: Layout/Mask Designer E3... ...Responsibilities Design and develop IP layouts used in DRAM chips. Perform... ...Knowledge of skill coding and layout automation. Self‑motivation, hard work, goal orientation...Sugerido
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Micron Memory Malaysia Sdn Bhd
Tlaquepaque, Jal.4 días atrás - ...Micron Technology, Inc in Tlaquepaque, Jalisco is seeking a DRAM Design Tech Layout Engineer to contribute to the design and development of IP layouts for DRAM chips. The role demands collaboration with global engineering teams and strong leadership in layout execution...Sugerido
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Micron Technology, Inc
Tlaquepaque, Jal.15 horas atrás
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